1. Field of the Invention
The present invention relates to a storage circuitry and method for propagating data values across a clock boundary.
2. Description of the Prior Art
It is known to use storage structures such as FIFOs (First-In-First-Out storage) to propagate data values across a clock boundary between a first clock domain and a second clock domain. The storage circuitry incorporating such a FIFO (or other storage structure) is often referred to as an asynchronous storage circuit, since data is typically written into the FIFO asynchronously to the reading of data from the FIFO. For the purposes of the present application, the first and second clock domains will be considered to be asynchronous not only in situations the clock edges in the first clock domain are generally unaligned with the clock edges in the second clock domain (for example where the clock frequencies in the two clock domains are unrelated), but also in situations where the clock frequency in one clock domain is an integer multiple of the clock frequency in the other clock domain and certain clock edges are aligned.
A write pointer is typically used to identify an entry in the FIFO to be written to, and similarly a read pointer is used to identify an entry to be read from. In accordance with the conventional technique, when queuing data in the FIFO for propagation across the clock boundary, the data is written into the FIFO using a current write pointer value, and at the same time that write pointer value is incremented, with the incremented version of the write pointer then being propagated across the clock boundary to read circuitry in order to allow the read circuitry to determine that there is data to be read from the FIFO. By incrementing the write pointer at the same time that write data is written into the FIFO, this ensures that when the read circuitry within the storage circuitry reads the data from the FIFO, that data will be valid and stable. In particular, on the read side, by the time it is perceived that the write pointer has changed, it will be guaranteed that the write data is available to be read.
However, in order for the read circuitry to correctly capture the write pointer, it must first be passed through write pointer synchronisation circuitry to reduce the probability of metastability in the write pointer, that could otherwise arise due to the differences between the clocks of the first and second clock domains (the write pointer having been incremented in the first clock domain, but then sampled by the read circuitry in the second clock domain).
At the relatively high frequencies (1.5 GHz and above) that are used in current process technologies, such write pointer synchronisation circuitry may be 3 or 4 flops long in order to reduce the probability of metastability to a satisfactory degree, and due to this the use of asynchronous storage circuits can be very expensive from a latency perspective.
Some research has been undertaken with respect to the design of the write pointer synchronisation circuitry, with the aim of trying to optimise the synchronising circuitry and thus reduce the latency, see for example the paper entitled “Low latency synchronization through speculation” by A Kinniment et al, Proceedings of the 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2004, pages 278-288. However, such techniques can be costly and complex, and accordingly it would be desirable to provide an alternative mechanism for improving the performance of such storage circuits including write pointer synchronisation circuitry.